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Sahithyan's S2
Sahithyan's S2 — Computer Organization and Digital Design

D Latch

Aka. data or delay latch. Has 2 inputs: DD and EnEn. Has 1 output: QQ. An extension of SR latch. Can be made with NAND or NOR gates.

EnDQQN

When EnEn is LOW, QQ is the stored value. When EnEn is HIGH, Q=DQ=D. If NOR gates were used instead, a NOT gate will be added to the EnEn input, and NOT gate of D input will be switched.

Generally less common than D flip-flops in modern synchronous designs due to their level-sensitive behavior which can lead to timing issues.

Truth Table

En\text{En}DDQnextQ_\text{next}
0xQ
100
111