Sahithyan's S2 — Computer Organization and Digital Design
D Latch
Aka. data or delay latch. Has 2 inputs: and . Has 1 output: . An extension of SR latch. Can be made with NAND or NOR gates.
When is LOW, is the stored value. When is HIGH, . If NOR gates were used instead, a NOT gate will be added to the input, and NOT gate of D input will be switched.
Generally less common than D flip-flops in modern synchronous designs due to their level-sensitive behavior which can lead to timing issues.
Truth Table
0 | x | Q |
1 | 0 | 0 |
1 | 1 | 1 |