Sahithyan's S2 — Computer Organization and Digital Design
D Flip-flop
Aka. data or delay flip-flop. Input is captured at rising edges of clock. Has 2
inputs:
To build a D flip-flop that’s triggered by falling edge of clock, the first NOT gate should be removed.
Characteristics
Characteristic tabl
| D | Clk | Comment |
|---|---|---|
| 0 | ↑ | Reset |
| 1 | ↑ | Set |
| X | 0 | No change |
| X | 1 | No change |
Excitation table
| Current State (Q) | Next State (Q+) | D |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |