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Sahithyan's S2
Sahithyan's S2 — Computer Organization and Digital Design

Memory

Consists of RAM and secondary memory.

In Von Neumann architecture, both data and instructions are stored in the same memory. In Howard Aiken’s architecture, data and instructions are stored in separate memories.

Memory cell

Basic element of a semiconductor memory. Carries two stable states: 1 and 0. State can be read or written.

Memory chip

Contains a 2D array of memory cells. A memory chip’s size is mentioned as "M×NbitM \times N\,\text{bit}". MM is the number of words, and NN is the size of a word.

Word

Number of bits written to/read from a chip simultaneously.

Memory module

Collection of memory chips.

Memory module organization

Memory types

RAM

Volatile. High-speed read and write. Can either be dynamic (built using capacitors) or static (built using flip flops).

  • SRAM: built using flip flops. expensive. faster. used for caching.
  • DRAM: built using capacitors. cheaper. slower. used for main memory. needs constant refreshing.

ROM

Non-volatile memory.

Memory TypeCategoryErasureWrite Mechanism
Read-only memory (ROM)Read-onlyNot possibleMasks
Programmable ROM (PROM)Read-onlyNot possibleElectrically
Erasable PROM (EPROM)Read-mostlyUV light, chip-levelElectrically
Electrically Erasable PROM (EEPROM)Read-mostlyElectrically, byte-levelElectrically
Flash memoryRead-mostlyElectrically, block-levelElectrically

Designing a memory module

For example, to build a 256K×8bit256\text{K}\times 8\,\text{bit} module with 256K×1bit256\text{K}\times 1\,\text{bit} chips:

  • Total number of chips required: (256×210×8)/(256×210×1)=8(256 \times 2^{10} \times 8) / (256 \times 2^{10} \times 1) = 8 chips
  • Size of address space: 256×210256\times 2^{10} addresses
  • Number of bits for address bus: 1818 bits